lo-lapack-proto.h File Reference

#include "octave-config.h"
#include "f77-fcn.h"
#include "oct-cmplx.h"

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Typedefs
typedef octave_idx_type(*	complex_selector )(const Complex &)
typedef octave_idx_type(*	double_selector )(const double &, const double &)
typedef octave_idx_type(*	float_complex_selector )(const FloatComplex &)
typedef octave_idx_type(*	float_selector )(const float &, const float &)

Functions
F77_RET_T	F77_FUNC (dgbcon, DGBCON)(F77_CONST_CHAR_ARG_DECL
F77_RET_T	F77_FUNC (zgbcon, ZGBCON)(F77_CONST_CHAR_ARG_DECL
F77_RET_T	F77_FUNC (dgbtrf, DGBTRF)(const F77_INT &
F77_RET_T const F77_INT const F77_INT const F77_INT F77_DBLE const F77_INT F77_INT F77_INT &F77_RET_T	F77_FUNC (zgbtrf, ZGBTRF)(const F77_INT &
F77_RET_T const F77_INT const F77_INT const F77_INT F77_DBLE const F77_INT F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_INT F77_INT &F77_RET_T	F77_FUNC (dgbtrs, DGBTRS)(F77_CONST_CHAR_ARG_DECL
F77_RET_T	F77_FUNC (zgbtrs, ZGBTRS)(F77_CONST_CHAR_ARG_DECL
F77_RET_T	F77_FUNC (cgebal, CGEBAL)(F77_CONST_CHAR_ARG_DECL
F77_RET_T	F77_FUNC (dgebal, DGEBAL)(F77_CONST_CHAR_ARG_DECL
F77_RET_T	F77_FUNC (sgebal, SGEBAL)(F77_CONST_CHAR_ARG_DECL
F77_RET_T	F77_FUNC (zgebal, ZGEBAL)(F77_CONST_CHAR_ARG_DECL
F77_RET_T	F77_FUNC (cgebak, CGEBAK)(F77_CONST_CHAR_ARG_DECL
F77_RET_T	F77_FUNC (dgebak, DGEBAK)(F77_CONST_CHAR_ARG_DECL
F77_RET_T	F77_FUNC (sgebak, SGEBAK)(F77_CONST_CHAR_ARG_DECL
F77_RET_T	F77_FUNC (zgebak, ZGEBAK)(F77_CONST_CHAR_ARG_DECL
F77_RET_T	F77_FUNC (cgecon, CGECON)(F77_CONST_CHAR_ARG_DECL
F77_RET_T	F77_FUNC (dgecon, DGECON)(F77_CONST_CHAR_ARG_DECL
F77_RET_T	F77_FUNC (sgecon, SGECON)(F77_CONST_CHAR_ARG_DECL
F77_RET_T	F77_FUNC (zgecon, ZGECON)(F77_CONST_CHAR_ARG_DECL
F77_RET_T	F77_FUNC (cgehrd, CGEHRD)(const F77_INT &
F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX const F77_INT F77_INT &F77_RET_T	F77_FUNC (dgehrd, DGEHRD)(const F77_INT &
F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX const F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE const F77_INT F77_INT &F77_RET_T	F77_FUNC (sgehrd, SGEHRD)(const F77_INT &
F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX const F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE const F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL const F77_INT F77_INT &F77_RET_T	F77_FUNC (zgehrd, ZGEHRD)(const F77_INT &
F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX const F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE const F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL const F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE_CMPLX const F77_INT F77_INT &F77_RET_T	F77_FUNC (cgeqp3, CGEQP3)(const F77_INT &
F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX const F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE const F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL const F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE_CMPLX const F77_INT F77_INT &F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_INT F77_CMPLX F77_CMPLX const F77_INT F77_REAL F77_INT &F77_RET_T	F77_FUNC (dgeqp3, DGEQP3)(const F77_INT &
F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX const F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE const F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL const F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE_CMPLX const F77_INT F77_INT &F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_INT F77_CMPLX F77_CMPLX const F77_INT F77_REAL F77_INT &F77_RET_T const F77_INT F77_DBLE const F77_INT F77_INT F77_DBLE F77_DBLE const F77_INT F77_INT &F77_RET_T	F77_FUNC (sgeqp3, SGEQP3)(const F77_INT &
F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX const F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE const F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL const F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE_CMPLX const F77_INT F77_INT &F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_INT F77_CMPLX F77_CMPLX const F77_INT F77_REAL F77_INT &F77_RET_T const F77_INT F77_DBLE const F77_INT F77_INT F77_DBLE F77_DBLE const F77_INT F77_INT &F77_RET_T const F77_INT F77_REAL const F77_INT F77_INT F77_REAL F77_REAL const F77_INT F77_INT &F77_RET_T	F77_FUNC (zgeqp3, ZGEQP3)(const F77_INT &
F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX const F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE const F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL const F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE_CMPLX const F77_INT F77_INT &F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_INT F77_CMPLX F77_CMPLX const F77_INT F77_REAL F77_INT &F77_RET_T const F77_INT F77_DBLE const F77_INT F77_INT F77_DBLE F77_DBLE const F77_INT F77_INT &F77_RET_T const F77_INT F77_REAL const F77_INT F77_INT F77_REAL F77_REAL const F77_INT F77_INT &F77_RET_T const F77_INT F77_DBLE_CMPLX const F77_INT F77_INT F77_DBLE_CMPLX F77_DBLE_CMPLX const F77_INT F77_DBLE F77_INT &F77_RET_T	F77_FUNC (cgeqrf, CGEQRF)(const F77_INT &
F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX const F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE const F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL const F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE_CMPLX const F77_INT F77_INT &F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_INT F77_CMPLX F77_CMPLX const F77_INT F77_REAL F77_INT &F77_RET_T const F77_INT F77_DBLE const F77_INT F77_INT F77_DBLE F77_DBLE const F77_INT F77_INT &F77_RET_T const F77_INT F77_REAL const F77_INT F77_INT F77_REAL F77_REAL const F77_INT F77_INT &F77_RET_T const F77_INT F77_DBLE_CMPLX const F77_INT F77_INT F77_DBLE_CMPLX F77_DBLE_CMPLX const F77_INT F77_DBLE F77_INT &F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX const F77_INT F77_INT &F77_RET_T	F77_FUNC (dgeqrf, DGEQRF)(const F77_INT &
F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX const F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE const F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL const F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE_CMPLX const F77_INT F77_INT &F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_INT F77_CMPLX F77_CMPLX const F77_INT F77_REAL F77_INT &F77_RET_T const F77_INT F77_DBLE const F77_INT F77_INT F77_DBLE F77_DBLE const F77_INT F77_INT &F77_RET_T const F77_INT F77_REAL const F77_INT F77_INT F77_REAL F77_REAL const F77_INT F77_INT &F77_RET_T const F77_INT F77_DBLE_CMPLX const F77_INT F77_INT F77_DBLE_CMPLX F77_DBLE_CMPLX const F77_INT F77_DBLE F77_INT &F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX const F77_INT F77_INT &F77_RET_T const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE const F77_INT F77_INT &F77_RET_T	F77_FUNC (sgeqrf, SGEQRF)(const F77_INT &
F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX const F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE const F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL const F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE_CMPLX const F77_INT F77_INT &F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_INT F77_CMPLX F77_CMPLX const F77_INT F77_REAL F77_INT &F77_RET_T const F77_INT F77_DBLE const F77_INT F77_INT F77_DBLE F77_DBLE const F77_INT F77_INT &F77_RET_T const F77_INT F77_REAL const F77_INT F77_INT F77_REAL F77_REAL const F77_INT F77_INT &F77_RET_T const F77_INT F77_DBLE_CMPLX const F77_INT F77_INT F77_DBLE_CMPLX F77_DBLE_CMPLX const F77_INT F77_DBLE F77_INT &F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX const F77_INT F77_INT &F77_RET_T const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE const F77_INT F77_INT &F77_RET_T const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL const F77_INT F77_INT &F77_RET_T	F77_FUNC (zgeqrf, ZGEQRF)(const F77_INT &
F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX const F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE const F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL const F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE_CMPLX const F77_INT F77_INT &F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_INT F77_CMPLX F77_CMPLX const F77_INT F77_REAL F77_INT &F77_RET_T const F77_INT F77_DBLE const F77_INT F77_INT F77_DBLE F77_DBLE const F77_INT F77_INT &F77_RET_T const F77_INT F77_REAL const F77_INT F77_INT F77_REAL F77_REAL const F77_INT F77_INT &F77_RET_T const F77_INT F77_DBLE_CMPLX const F77_INT F77_INT F77_DBLE_CMPLX F77_DBLE_CMPLX const F77_INT F77_DBLE F77_INT &F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX const F77_INT F77_INT &F77_RET_T const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE const F77_INT F77_INT &F77_RET_T const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL const F77_INT F77_INT &F77_RET_T const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE_CMPLX const F77_INT F77_INT &F77_RET_T	F77_FUNC (cgesdd, CGESDD)(F77_CONST_CHAR_ARG_DECL
F77_RET_T	F77_FUNC (dgesdd, DGESDD)(F77_CONST_CHAR_ARG_DECL
F77_RET_T	F77_FUNC (sgesdd, SGESDD)(F77_CONST_CHAR_ARG_DECL
F77_RET_T	F77_FUNC (zgesdd, ZGESDD)(F77_CONST_CHAR_ARG_DECL
F77_RET_T	F77_FUNC (cgesvd, CGESVD)(F77_CONST_CHAR_ARG_DECL
F77_RET_T	F77_FUNC (dgesvd, DGESVD)(F77_CONST_CHAR_ARG_DECL
F77_RET_T	F77_FUNC (sgesvd, SGESVD)(F77_CONST_CHAR_ARG_DECL
F77_RET_T	F77_FUNC (zgesvd, ZGESVD)(F77_CONST_CHAR_ARG_DECL
F77_RET_T	F77_FUNC (cgeesx, CGEESX)(F77_CONST_CHAR_ARG_DECL
F77_RET_T	F77_FUNC (dgeesx, DGEESX)(F77_CONST_CHAR_ARG_DECL
F77_RET_T	F77_FUNC (sgeesx, SGEESX)(F77_CONST_CHAR_ARG_DECL
F77_RET_T	F77_FUNC (zgeesx, ZGEESX)(F77_CONST_CHAR_ARG_DECL
F77_RET_T	F77_FUNC (cgeevx, CGEEVX)(F77_CONST_CHAR_ARG_DECL
F77_RET_T	F77_FUNC (dgeevx, DGEEVX)(F77_CONST_CHAR_ARG_DECL
F77_RET_T	F77_FUNC (sgeevx, SGEEVX)(F77_CONST_CHAR_ARG_DECL
F77_RET_T	F77_FUNC (zgeevx, ZGEEVX)(F77_CONST_CHAR_ARG_DECL
F77_RET_T	F77_FUNC (cgelsd, CGELSD)(const F77_INT &
F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_REAL F77_REAL F77_INT F77_CMPLX const F77_INT F77_REAL F77_INT F77_INT &F77_RET_T	F77_FUNC (dgelsd, DGELSD)(const F77_INT &
F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_REAL F77_REAL F77_INT F77_CMPLX const F77_INT F77_REAL F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT F77_DBLE const F77_INT F77_INT F77_INT &F77_RET_T	F77_FUNC (sgelsd, SGELSD)(const F77_INT &
F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_REAL F77_REAL F77_INT F77_CMPLX const F77_INT F77_REAL F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT F77_DBLE const F77_INT F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL F77_INT F77_REAL const F77_INT F77_INT F77_INT &F77_RET_T	F77_FUNC (zgelsd, ZGELSD)(const F77_INT &
F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_REAL F77_REAL F77_INT F77_CMPLX const F77_INT F77_REAL F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT F77_DBLE const F77_INT F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL F77_INT F77_REAL const F77_INT F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE F77_DBLE F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE F77_INT F77_INT &F77_RET_T	F77_FUNC (cgelsy, CGELSY)(const F77_INT &
F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_REAL F77_REAL F77_INT F77_CMPLX const F77_INT F77_REAL F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT F77_DBLE const F77_INT F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL F77_INT F77_REAL const F77_INT F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE F77_DBLE F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_INT F77_REAL F77_INT F77_CMPLX const F77_INT F77_REAL F77_INT &F77_RET_T	F77_FUNC (dgelsy, DGELSY)(const F77_INT &
F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_REAL F77_REAL F77_INT F77_CMPLX const F77_INT F77_REAL F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT F77_DBLE const F77_INT F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL F77_INT F77_REAL const F77_INT F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE F77_DBLE F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_INT F77_REAL F77_INT F77_CMPLX const F77_INT F77_REAL F77_INT &F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_INT F77_DBLE F77_INT F77_DBLE const F77_INT F77_INT &F77_RET_T	F77_FUNC (sgelsy, SGELSY)(const F77_INT &
F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_REAL F77_REAL F77_INT F77_CMPLX const F77_INT F77_REAL F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT F77_DBLE const F77_INT F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL F77_INT F77_REAL const F77_INT F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE F77_DBLE F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_INT F77_REAL F77_INT F77_CMPLX const F77_INT F77_REAL F77_INT &F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_INT F77_DBLE F77_INT F77_DBLE const F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_INT F77_REAL F77_INT F77_REAL const F77_INT F77_INT &F77_RET_T	F77_FUNC (zgelsy, ZGELSY)(const F77_INT &
F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_REAL F77_REAL F77_INT F77_CMPLX const F77_INT F77_REAL F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT F77_DBLE const F77_INT F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL F77_INT F77_REAL const F77_INT F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE F77_DBLE F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_INT F77_REAL F77_INT F77_CMPLX const F77_INT F77_REAL F77_INT &F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_INT F77_DBLE F77_INT F77_DBLE const F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_INT F77_REAL F77_INT F77_REAL const F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_INT F77_DBLE F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE F77_INT &F77_RET_T	F77_FUNC (cgetrf, CGETRF)(const F77_INT &
F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_REAL F77_REAL F77_INT F77_CMPLX const F77_INT F77_REAL F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT F77_DBLE const F77_INT F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL F77_INT F77_REAL const F77_INT F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE F77_DBLE F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_INT F77_REAL F77_INT F77_CMPLX const F77_INT F77_REAL F77_INT &F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_INT F77_DBLE F77_INT F77_DBLE const F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_INT F77_REAL F77_INT F77_REAL const F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_INT F77_DBLE F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE F77_INT &F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_INT F77_INT &F77_RET_T	F77_FUNC (dgetrf, DGETRF)(const F77_INT &
F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_REAL F77_REAL F77_INT F77_CMPLX const F77_INT F77_REAL F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT F77_DBLE const F77_INT F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL F77_INT F77_REAL const F77_INT F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE F77_DBLE F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_INT F77_REAL F77_INT F77_CMPLX const F77_INT F77_REAL F77_INT &F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_INT F77_DBLE F77_INT F77_DBLE const F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_INT F77_REAL F77_INT F77_REAL const F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_INT F77_DBLE F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE F77_INT &F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_INT F77_INT &F77_RET_T const F77_INT F77_DBLE const F77_INT F77_INT F77_INT &F77_RET_T	F77_FUNC (sgetrf, SGETRF)(const F77_INT &
F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_REAL F77_REAL F77_INT F77_CMPLX const F77_INT F77_REAL F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT F77_DBLE const F77_INT F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL F77_INT F77_REAL const F77_INT F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE F77_DBLE F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_INT F77_REAL F77_INT F77_CMPLX const F77_INT F77_REAL F77_INT &F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_INT F77_DBLE F77_INT F77_DBLE const F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_INT F77_REAL F77_INT F77_REAL const F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_INT F77_DBLE F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE F77_INT &F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_INT F77_INT &F77_RET_T const F77_INT F77_DBLE const F77_INT F77_INT F77_INT &F77_RET_T const F77_INT F77_REAL const F77_INT F77_INT F77_INT &F77_RET_T	F77_FUNC (zgetrf, ZGETRF)(const F77_INT &
F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_REAL F77_REAL F77_INT F77_CMPLX const F77_INT F77_REAL F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT F77_DBLE const F77_INT F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL F77_INT F77_REAL const F77_INT F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE F77_DBLE F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_INT F77_REAL F77_INT F77_CMPLX const F77_INT F77_REAL F77_INT &F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_INT F77_DBLE F77_INT F77_DBLE const F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_INT F77_REAL F77_INT F77_REAL const F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_INT F77_DBLE F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE F77_INT &F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_INT F77_INT &F77_RET_T const F77_INT F77_DBLE const F77_INT F77_INT F77_INT &F77_RET_T const F77_INT F77_REAL const F77_INT F77_INT F77_INT &F77_RET_T const F77_INT F77_DBLE_CMPLX const F77_INT F77_INT F77_INT &F77_RET_T	F77_FUNC (cgetri, CGETRI)(const F77_INT &
F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_REAL F77_REAL F77_INT F77_CMPLX const F77_INT F77_REAL F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT F77_DBLE const F77_INT F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL F77_INT F77_REAL const F77_INT F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE F77_DBLE F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_INT F77_REAL F77_INT F77_CMPLX const F77_INT F77_REAL F77_INT &F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_INT F77_DBLE F77_INT F77_DBLE const F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_INT F77_REAL F77_INT F77_REAL const F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_INT F77_DBLE F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE F77_INT &F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_INT F77_INT &F77_RET_T const F77_INT F77_DBLE const F77_INT F77_INT F77_INT &F77_RET_T const F77_INT F77_REAL const F77_INT F77_INT F77_INT &F77_RET_T const F77_INT F77_DBLE_CMPLX const F77_INT F77_INT F77_INT &F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_CMPLX const F77_INT F77_INT &F77_RET_T	F77_FUNC (dgetri, DGETRI)(const F77_INT &
F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_REAL F77_REAL F77_INT F77_CMPLX const F77_INT F77_REAL F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT F77_DBLE const F77_INT F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL F77_INT F77_REAL const F77_INT F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE F77_DBLE F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_INT F77_REAL F77_INT F77_CMPLX const F77_INT F77_REAL F77_INT &F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_INT F77_DBLE F77_INT F77_DBLE const F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_INT F77_REAL F77_INT F77_REAL const F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_INT F77_DBLE F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE F77_INT &F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_INT F77_INT &F77_RET_T const F77_INT F77_DBLE const F77_INT F77_INT F77_INT &F77_RET_T const F77_INT F77_REAL const F77_INT F77_INT F77_INT &F77_RET_T const F77_INT F77_DBLE_CMPLX const F77_INT F77_INT F77_INT &F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_CMPLX const F77_INT F77_INT &F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE const F77_INT F77_INT &F77_RET_T	F77_FUNC (sgetri, SGETRI)(const F77_INT &
F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_REAL F77_REAL F77_INT F77_CMPLX const F77_INT F77_REAL F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT F77_DBLE const F77_INT F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL F77_INT F77_REAL const F77_INT F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE F77_DBLE F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_INT F77_REAL F77_INT F77_CMPLX const F77_INT F77_REAL F77_INT &F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_INT F77_DBLE F77_INT F77_DBLE const F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_INT F77_REAL F77_INT F77_REAL const F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_INT F77_DBLE F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE F77_INT &F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_INT F77_INT &F77_RET_T const F77_INT F77_DBLE const F77_INT F77_INT F77_INT &F77_RET_T const F77_INT F77_REAL const F77_INT F77_INT F77_INT &F77_RET_T const F77_INT F77_DBLE_CMPLX const F77_INT F77_INT F77_INT &F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_CMPLX const F77_INT F77_INT &F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE const F77_INT F77_INT &F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL const F77_INT F77_INT &F77_RET_T	F77_FUNC (zgetri, ZGETRI)(const F77_INT &
F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_REAL F77_REAL F77_INT F77_CMPLX const F77_INT F77_REAL F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT F77_DBLE const F77_INT F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL F77_INT F77_REAL const F77_INT F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE F77_DBLE F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_INT F77_REAL F77_INT F77_CMPLX const F77_INT F77_REAL F77_INT &F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_INT F77_DBLE F77_INT F77_DBLE const F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_INT F77_REAL F77_INT F77_REAL const F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_INT F77_DBLE F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE F77_INT &F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_INT F77_INT &F77_RET_T const F77_INT F77_DBLE const F77_INT F77_INT F77_INT &F77_RET_T const F77_INT F77_REAL const F77_INT F77_INT F77_INT &F77_RET_T const F77_INT F77_DBLE_CMPLX const F77_INT F77_INT F77_INT &F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_CMPLX const F77_INT F77_INT &F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE const F77_INT F77_INT &F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL const F77_INT F77_INT &F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_INT &F77_RET_T	F77_FUNC (cgetrs, CGETRS)(F77_CONST_CHAR_ARG_DECL
F77_RET_T	F77_FUNC (dgetrs, DGETRS)(F77_CONST_CHAR_ARG_DECL
F77_RET_T	F77_FUNC (sgetrs, SGETRS)(F77_CONST_CHAR_ARG_DECL
F77_RET_T	F77_FUNC (zgetrs, ZGETRS)(F77_CONST_CHAR_ARG_DECL
F77_RET_T	F77_FUNC (cggbal, CGGBAL)(F77_CONST_CHAR_ARG_DECL
F77_RET_T	F77_FUNC (dggbal, DGGBAL)(F77_CONST_CHAR_ARG_DECL
F77_RET_T	F77_FUNC (sggbal, SGGBAL)(F77_CONST_CHAR_ARG_DECL
F77_RET_T	F77_FUNC (zggbal, ZGGBAL)(F77_CONST_CHAR_ARG_DECL
F77_RET_T	F77_FUNC (dggbak, DGGBAK)(F77_CONST_CHAR_ARG_DECL
F77_RET_T	F77_FUNC (sggbak, SGGBAK)(F77_CONST_CHAR_ARG_DECL
F77_RET_T	F77_FUNC (zggbak, ZGGBAK)(F77_CONST_CHAR_ARG_DECL
F77_RET_T	F77_FUNC (cggev, CGGEV)(F77_CONST_CHAR_ARG_DECL
F77_RET_T	F77_FUNC (dggev, DGGEV)(F77_CONST_CHAR_ARG_DECL
F77_RET_T	F77_FUNC (sggev, SGGEV)(F77_CONST_CHAR_ARG_DECL
F77_RET_T	F77_FUNC (zggev, ZGGEV)(F77_CONST_CHAR_ARG_DECL
F77_RET_T	F77_FUNC (dgghrd, DGGHRD)(F77_CONST_CHAR_ARG_DECL
F77_RET_T	F77_FUNC (zgghrd, ZGGHRD)(F77_CONST_CHAR_ARG_DECL
F77_RET_T	F77_FUNC (dgtsv, DGTSV)(const F77_INT &
F77_RET_T const F77_INT F77_DBLE F77_DBLE F77_DBLE F77_DBLE const F77_INT F77_INT &F77_RET_T	F77_FUNC (zgtsv, ZGTSV)(const F77_INT &
F77_RET_T const F77_INT F77_DBLE F77_DBLE F77_DBLE F77_DBLE const F77_INT F77_INT &F77_RET_T const F77_INT F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE_CMPLX const F77_INT F77_INT &F77_RET_T	F77_FUNC (dgttrf, DGTTRF)(const F77_INT &
F77_RET_T const F77_INT F77_DBLE F77_DBLE F77_DBLE F77_DBLE const F77_INT F77_INT &F77_RET_T const F77_INT F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE_CMPLX const F77_INT F77_INT &F77_RET_T F77_DBLE F77_DBLE F77_DBLE F77_DBLE F77_INT F77_INT &F77_RET_T	F77_FUNC (zgttrf, ZGTTRF)(const F77_INT &
F77_RET_T const F77_INT F77_DBLE F77_DBLE F77_DBLE F77_DBLE const F77_INT F77_INT &F77_RET_T const F77_INT F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE_CMPLX const F77_INT F77_INT &F77_RET_T F77_DBLE F77_DBLE F77_DBLE F77_DBLE F77_INT F77_INT &F77_RET_T F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE_CMPLX F77_INT F77_INT &F77_RET_T	F77_FUNC (dgttrs, DGTTRS)(F77_CONST_CHAR_ARG_DECL
F77_RET_T	F77_FUNC (zgttrs, ZGTTRS)(F77_CONST_CHAR_ARG_DECL
F77_RET_T	F77_FUNC (cheev, CHEEV)(F77_CONST_CHAR_ARG_DECL
F77_RET_T	F77_FUNC (zheev, ZHEEV)(F77_CONST_CHAR_ARG_DECL
F77_RET_T	F77_FUNC (chegv, CHEGV)(const F77_INT &
F77_RET_T	F77_FUNC (zhegv, ZHEGV)(const F77_INT &
F77_RET_T	F77_FUNC (cherk, CHERK)(F77_CONST_CHAR_ARG_DECL
F77_RET_T	F77_FUNC (zherk, ZHERK)(F77_CONST_CHAR_ARG_DECL
F77_RET_T	F77_FUNC (dhgeqz, DHGEQZ)(F77_CONST_CHAR_ARG_DECL
F77_RET_T	F77_FUNC (zhgeqz, ZHGEQZ)(F77_CONST_CHAR_ARG_DECL
F77_RET_T	F77_FUNC (xilaenv, XILAENV)(const F77_INT &
F77_RET_T	F77_FUNC (dlag2, DLAG2)(const F77_DBLE *A
F77_RET_T	F77_FUNC (xdlamch, XDLAMCH)(F77_CONST_CHAR_ARG_DECL
F77_RET_T	F77_FUNC (xclange, XCLANGE)(F77_CONST_CHAR_ARG_DECL
F77_RET_T	F77_FUNC (xdlange, XDLANGE)(F77_CONST_CHAR_ARG_DECL
F77_RET_T	F77_FUNC (xslange, XSLANGE)(F77_CONST_CHAR_ARG_DECL
F77_RET_T	F77_FUNC (xzlange, XZLANGE)(F77_CONST_CHAR_ARG_DECL
F77_RET_T	F77_FUNC (clartg, CLARTG)(const F77_CMPLX *
F77_RET_T const F77_CMPLX F77_REAL F77_CMPLX F77_CMPLX *F77_RET_T	F77_FUNC (dlartg, DLARTG)(const F77_DBLE &
F77_RET_T const F77_CMPLX F77_REAL F77_CMPLX F77_CMPLX *F77_RET_T const F77_DBLE F77_DBLE F77_DBLE F77_DBLE &F77_RET_T	F77_FUNC (slartg, SLARTG)(const F77_REAL &
F77_RET_T const F77_CMPLX F77_REAL F77_CMPLX F77_CMPLX *F77_RET_T const F77_DBLE F77_DBLE F77_DBLE F77_DBLE &F77_RET_T const F77_REAL F77_REAL F77_REAL F77_REAL &F77_RET_T	F77_FUNC (zlartg, ZLARTG)(const F77_DBLE_CMPLX *
F77_RET_T const F77_CMPLX F77_REAL F77_CMPLX F77_CMPLX *F77_RET_T const F77_DBLE F77_DBLE F77_DBLE F77_DBLE &F77_RET_T const F77_REAL F77_REAL F77_REAL F77_REAL &F77_RET_T const F77_DBLE_CMPLX F77_DBLE F77_DBLE_CMPLX F77_DBLE_CMPLX *F77_RET_T	F77_FUNC (dorghr, DORGHR)(const F77_INT &
F77_RET_T const F77_CMPLX F77_REAL F77_CMPLX F77_CMPLX *F77_RET_T const F77_DBLE F77_DBLE F77_DBLE F77_DBLE &F77_RET_T const F77_REAL F77_REAL F77_REAL F77_REAL &F77_RET_T const F77_DBLE_CMPLX F77_DBLE F77_DBLE_CMPLX F77_DBLE_CMPLX *F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE const F77_INT F77_INT &F77_RET_T	F77_FUNC (sorghr, SORGHR)(const F77_INT &
F77_RET_T const F77_CMPLX F77_REAL F77_CMPLX F77_CMPLX *F77_RET_T const F77_DBLE F77_DBLE F77_DBLE F77_DBLE &F77_RET_T const F77_REAL F77_REAL F77_REAL F77_REAL &F77_RET_T const F77_DBLE_CMPLX F77_DBLE F77_DBLE_CMPLX F77_DBLE_CMPLX *F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE const F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL const F77_INT F77_INT &F77_RET_T	F77_FUNC (dorgqr, DORGQR)(const F77_INT &
F77_RET_T const F77_CMPLX F77_REAL F77_CMPLX F77_CMPLX *F77_RET_T const F77_DBLE F77_DBLE F77_DBLE F77_DBLE &F77_RET_T const F77_REAL F77_REAL F77_REAL F77_REAL &F77_RET_T const F77_DBLE_CMPLX F77_DBLE F77_DBLE_CMPLX F77_DBLE_CMPLX *F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE const F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL const F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE const F77_INT F77_INT &F77_RET_T	F77_FUNC (sorgqr, SORGQR)(const F77_INT &
F77_RET_T const F77_CMPLX F77_REAL F77_CMPLX F77_CMPLX *F77_RET_T const F77_DBLE F77_DBLE F77_DBLE F77_DBLE &F77_RET_T const F77_REAL F77_REAL F77_REAL F77_REAL &F77_RET_T const F77_DBLE_CMPLX F77_DBLE F77_DBLE_CMPLX F77_DBLE_CMPLX *F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE const F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL const F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE const F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL const F77_INT F77_INT &F77_RET_T	F77_FUNC (dpbcon, DPBCON)(F77_CONST_CHAR_ARG_DECL
F77_RET_T	F77_FUNC (zpbcon, ZPBCON)(F77_CONST_CHAR_ARG_DECL
F77_RET_T	F77_FUNC (dpbtrf, DPBTRF)(F77_CONST_CHAR_ARG_DECL
F77_RET_T	F77_FUNC (zpbtrf, ZPBTRF)(F77_CONST_CHAR_ARG_DECL
F77_RET_T	F77_FUNC (dpbtrs, DPBTRS)(F77_CONST_CHAR_ARG_DECL
F77_RET_T	F77_FUNC (zpbtrs, ZPBTRS)(F77_CONST_CHAR_ARG_DECL
F77_RET_T	F77_FUNC (cpocon, CPOCON)(F77_CONST_CHAR_ARG_DECL
F77_RET_T	F77_FUNC (dpocon, DPOCON)(F77_CONST_CHAR_ARG_DECL
F77_RET_T	F77_FUNC (spocon, SPOCON)(F77_CONST_CHAR_ARG_DECL
F77_RET_T	F77_FUNC (zpocon, ZPOCON)(F77_CONST_CHAR_ARG_DECL
F77_RET_T	F77_FUNC (cpotrf, CPOTRF)(F77_CONST_CHAR_ARG_DECL
F77_RET_T	F77_FUNC (dpotrf, DPOTRF)(F77_CONST_CHAR_ARG_DECL
F77_RET_T	F77_FUNC (spotrf, SPOTRF)(F77_CONST_CHAR_ARG_DECL
F77_RET_T	F77_FUNC (zpotrf, ZPOTRF)(F77_CONST_CHAR_ARG_DECL
F77_RET_T	F77_FUNC (cpotri, CPOTRI)(F77_CONST_CHAR_ARG_DECL
F77_RET_T	F77_FUNC (dpotri, DPOTRI)(F77_CONST_CHAR_ARG_DECL
F77_RET_T	F77_FUNC (spotri, SPOTRI)(F77_CONST_CHAR_ARG_DECL
F77_RET_T	F77_FUNC (zpotri, ZPOTRI)(F77_CONST_CHAR_ARG_DECL
F77_RET_T	F77_FUNC (spotrs, SPOTRS)(F77_CONST_CHAR_ARG_DECL
F77_RET_T	F77_FUNC (cpotrs, CPOTRS)(F77_CONST_CHAR_ARG_DECL
F77_RET_T	F77_FUNC (dpotrs, DPOTRS)(F77_CONST_CHAR_ARG_DECL
F77_RET_T	F77_FUNC (zpotrs, ZPOTRS)(F77_CONST_CHAR_ARG_DECL
F77_RET_T	F77_FUNC (dptsv, DPTSV)(const F77_INT &
F77_RET_T const F77_INT F77_DBLE F77_DBLE F77_DBLE const F77_INT F77_INT &F77_RET_T	F77_FUNC (zptsv, ZPTSV)(const F77_INT &
F77_RET_T const F77_INT F77_DBLE F77_DBLE F77_DBLE const F77_INT F77_INT &F77_RET_T const F77_INT F77_DBLE F77_DBLE_CMPLX F77_DBLE_CMPLX const F77_INT F77_INT &F77_RET_T	F77_FUNC (zrsf2csf, ZRSF2CSF)(const F77_INT &
F77_RET_T const F77_INT F77_DBLE F77_DBLE F77_DBLE const F77_INT F77_INT &F77_RET_T const F77_INT F77_DBLE F77_DBLE_CMPLX F77_DBLE_CMPLX const F77_INT F77_INT &F77_RET_T F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE F77_DBLE *F77_RET_T	F77_FUNC (crsf2csf, CRSF2CSF)(const F77_INT &
F77_RET_T const F77_INT F77_DBLE F77_DBLE F77_DBLE const F77_INT F77_INT &F77_RET_T const F77_INT F77_DBLE F77_DBLE_CMPLX F77_DBLE_CMPLX const F77_INT F77_INT &F77_RET_T F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE F77_DBLE *F77_RET_T F77_CMPLX F77_CMPLX F77_REAL F77_REAL *F77_RET_T	F77_FUNC (dsyev, DSYEV)(F77_CONST_CHAR_ARG_DECL
F77_RET_T	F77_FUNC (ssyev, SSYEV)(F77_CONST_CHAR_ARG_DECL
F77_RET_T	F77_FUNC (dsygv, DSYGV)(const F77_INT &
F77_RET_T	F77_FUNC (ssygv, SSYGV)(const F77_INT &
F77_RET_T	F77_FUNC (csyrk, CSYRK)(F77_CONST_CHAR_ARG_DECL
F77_RET_T	F77_FUNC (dsyrk, DSYRK)(F77_CONST_CHAR_ARG_DECL
F77_RET_T	F77_FUNC (ssyrk, SSYRK)(F77_CONST_CHAR_ARG_DECL
F77_RET_T	F77_FUNC (zsyrk, ZSYRK)(F77_CONST_CHAR_ARG_DECL
F77_RET_T	F77_FUNC (dtgevc, DTGEVC)(F77_CONST_CHAR_ARG_DECL
F77_RET_T	F77_FUNC (ztgevc, ZTGEVC)(F77_CONST_CHAR_ARG_DECL
F77_RET_T	F77_FUNC (ctrcon, CTRCON)(F77_CONST_CHAR_ARG_DECL
F77_RET_T	F77_FUNC (dtrcon, DTRCON)(F77_CONST_CHAR_ARG_DECL
F77_RET_T	F77_FUNC (strcon, STRCON)(F77_CONST_CHAR_ARG_DECL
F77_RET_T	F77_FUNC (ztrcon, ZTRCON)(F77_CONST_CHAR_ARG_DECL
F77_RET_T	F77_FUNC (ctrsen, CTRSEN)(F77_CONST_CHAR_ARG_DECL
F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_INT F77_REAL F77_REAL F77_CMPLX const F77_INT F77_INT &F77_RET_T	F77_FUNC (dtrsen, DTRSEN)(F77_CONST_CHAR_ARG_DECL
F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_INT F77_REAL F77_REAL F77_CMPLX const F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT F77_DBLE F77_DBLE F77_DBLE const F77_INT F77_INT const F77_INT F77_INT &F77_RET_T	F77_FUNC (strsen, STRSEN)(F77_CONST_CHAR_ARG_DECL
F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_INT F77_REAL F77_REAL F77_CMPLX const F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT F77_DBLE F77_DBLE F77_DBLE const F77_INT F77_INT const F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL F77_INT F77_REAL F77_REAL F77_REAL const F77_INT F77_INT const F77_INT F77_INT &F77_RET_T	F77_FUNC (ztrsen, ZTRSEN)(F77_CONST_CHAR_ARG_DECL
F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_INT F77_REAL F77_REAL F77_CMPLX const F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT F77_DBLE F77_DBLE F77_DBLE const F77_INT F77_INT const F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL F77_INT F77_REAL F77_REAL F77_REAL const F77_INT F77_INT const F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_INT F77_DBLE F77_DBLE F77_DBLE_CMPLX const F77_INT F77_INT &F77_RET_T	F77_FUNC (ctrsyl, CTRSYL)(F77_CONST_CHAR_ARG_DECL
F77_RET_T	F77_FUNC (dtrsyl, DTRSYL)(F77_CONST_CHAR_ARG_DECL
F77_RET_T	F77_FUNC (strsyl, STRSYL)(F77_CONST_CHAR_ARG_DECL
F77_RET_T	F77_FUNC (ztrsyl, ZTRSYL)(F77_CONST_CHAR_ARG_DECL
F77_RET_T	F77_FUNC (ctrtri, CTRTRI)(F77_CONST_CHAR_ARG_DECL
F77_RET_T	F77_FUNC (dtrtri, DTRTRI)(F77_CONST_CHAR_ARG_DECL
F77_RET_T	F77_FUNC (strtri, STRTRI)(F77_CONST_CHAR_ARG_DECL
F77_RET_T	F77_FUNC (ztrtri, ZTRTRI)(F77_CONST_CHAR_ARG_DECL
F77_RET_T	F77_FUNC (ctrtrs, CTRTRS)(F77_CONST_CHAR_ARG_DECL
F77_RET_T	F77_FUNC (dtrtrs, DTRTRS)(F77_CONST_CHAR_ARG_DECL
F77_RET_T	F77_FUNC (strtrs, STRTRS)(F77_CONST_CHAR_ARG_DECL
F77_RET_T	F77_FUNC (ztrtrs, ZTRTRS)(F77_CONST_CHAR_ARG_DECL
F77_RET_T	F77_FUNC (cunghr, CUNGHR)(const F77_INT &
F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX const F77_INT F77_INT &F77_RET_T	F77_FUNC (zunghr, ZUNGHR)(const F77_INT &
F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX const F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE_CMPLX const F77_INT F77_INT &F77_RET_T	F77_FUNC (cungqr, CUNGQR)(const F77_INT &
F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX const F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE_CMPLX const F77_INT F77_INT &F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX const F77_INT F77_INT &F77_RET_T	F77_FUNC (zungqr, ZUNGQR)(const F77_INT &

Variables
F77_RET_T const F77_INT F77_CMPLX *	A
F77_RET_T const F77_INT const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX *	ALPHA
F77_RET_T const F77_INT const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE *	ALPHAI
F77_RET_T const F77_INT const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE *	ALPHAR
F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_CMPLX *	B
F77_RET_T const F77_INT const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_DBLE *	BETA
F77_RET_T const F77_INT const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE_CMPLX *	CQ
F77_RET_T F77_INT const F77_INT const F77_DBLE_CMPLX const F77_INT const F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT F77_INT F77_DBLE_CMPLX *	CWORK
F77_RET_T const F77_INT const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX *	CZ
F77_RET_T const F77_INT const F77_INT const F77_INT F77_DBLE const F77_INT const F77_INT const F77_DBLE F77_DBLE F77_DBLE F77_INT F77_INT &	F77_CHAR_ARG_LEN_DECL
F77_RET_T	F77_CONST_CHAR_ARG_DECL
F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_INT F77_INT &	IHI
F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_INT &	ILO
F77_RET_T const F77_INT F77_CMPLX const F77_INT &	LDA
F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT &	LDB
F77_RET_T const F77_INT const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT &	LDQ
F77_RET_T const F77_INT const F77_INT const F77_INT const F77_DBLE const F77_DBLE F77_INT F77_DBLE const F77_INT &	LDV
F77_RET_T F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT &	LDVL
F77_RET_T F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT &	LDVR
F77_RET_T const F77_INT const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT &	LDZ
F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_INT F77_INT F77_REAL *	LSCALE
F77_RET_T const F77_INT const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_DBLE F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT &	LWORK
F77_RET_T const F77_INT const F77_INT const F77_INT const F77_DBLE const F77_DBLE F77_INT &	M
F77_RET_T F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT &	MM
F77_RET_T const F77_INT &	N
F77_RET_T const F77_INT const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE *	Q
F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_INT F77_INT F77_REAL F77_REAL *	RSCALE
F77_RET_T const F77_INT const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE *	RWORK
F77_RET_T const F77_INT const F77_DBLE const F77_INT const F77_DBLE &	SAFMIN
F77_RET_T const F77_INT const F77_DBLE const F77_INT const F77_DBLE F77_DBLE &	SCALE1
F77_RET_T const F77_INT const F77_DBLE const F77_INT const F77_DBLE F77_DBLE F77_DBLE &	SCALE2
F77_RET_T F77_INT *	SELECT
F77_RET_T const F77_INT const F77_INT const F77_INT const F77_DBLE const F77_DBLE F77_INT F77_DBLE *	V
F77_RET_T F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE *	VL
F77_RET_T F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE *	VR
F77_RET_T const F77_INT const F77_DBLE const F77_INT const F77_DBLE F77_DBLE F77_DBLE F77_DBLE F77_DBLE F77_DBLE &	WI
F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_INT F77_INT F77_REAL F77_REAL F77_REAL *	WORK
F77_RET_T const F77_INT const F77_DBLE const F77_INT const F77_DBLE F77_DBLE F77_DBLE F77_DBLE &	WR1
F77_RET_T const F77_INT const F77_DBLE const F77_INT const F77_DBLE F77_DBLE F77_DBLE F77_DBLE F77_DBLE &	WR2
F77_RET_T F77_INT const F77_INT const F77_DBLE_CMPLX const F77_INT const F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX *	xVL
F77_RET_T F77_INT const F77_INT const F77_DBLE_CMPLX const F77_INT const F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX *	xVR
F77_RET_T const F77_INT const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE *	Z

Typedef Documentation

F77_RET_T complex_selector

Definition at line 359 of file lo-lapack-proto.h.

F77_RET_T double_selector

Definition at line 357 of file lo-lapack-proto.h.

F77_RET_T float_complex_selector

Definition at line 360 of file lo-lapack-proto.h.

F77_RET_T float_selector

Definition at line 358 of file lo-lapack-proto.h.

Function Documentation

F77_RET_T F77_FUNC	(	dgbcon	,
		DGBCON
	)

F77_RET_T F77_FUNC	(	zgbcon	,
		ZGBCON
	)

F77_RET_T F77_FUNC	(	dgbtrf	,
		DGBTRF
	)		const

F77_RET_T const F77_INT const F77_INT const F77_INT F77_DBLE const F77_INT F77_INT F77_INT& F77_RET_T F77_FUNC	(	zgbtrf	,
		ZGBTRF
	)		const

F77_RET_T const F77_INT const F77_INT const F77_INT F77_DBLE const F77_INT F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_INT F77_INT& F77_RET_T F77_FUNC	(	dgbtrs	,
		DGBTRS
	)

F77_RET_T F77_FUNC	(	zgbtrs	,
		ZGBTRS
	)

F77_RET_T F77_FUNC	(	cgebal	,
		CGEBAL
	)

F77_RET_T F77_FUNC	(	dgebal	,
		DGEBAL
	)

F77_RET_T F77_FUNC	(	sgebal	,
		SGEBAL
	)

F77_RET_T F77_FUNC	(	zgebal	,
		ZGEBAL
	)

F77_RET_T F77_FUNC	(	cgebak	,
		CGEBAK
	)

F77_RET_T F77_FUNC	(	dgebak	,
		DGEBAK
	)

F77_RET_T F77_FUNC	(	sgebak	,
		SGEBAK
	)

F77_RET_T F77_FUNC	(	zgebak	,
		ZGEBAK
	)

F77_RET_T F77_FUNC	(	cgecon	,
		CGECON
	)

F77_RET_T F77_FUNC	(	dgecon	,
		DGECON
	)

F77_RET_T F77_FUNC	(	sgecon	,
		SGECON
	)

F77_RET_T F77_FUNC	(	zgecon	,
		ZGECON
	)

F77_RET_T F77_FUNC	(	cgehrd	,
		CGEHRD
	)		const

F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX const F77_INT F77_INT& F77_RET_T F77_FUNC	(	dgehrd	,
		DGEHRD
	)		const

F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX const F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE const F77_INT F77_INT& F77_RET_T F77_FUNC	(	sgehrd	,
		SGEHRD
	)		const

F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX const F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE const F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL const F77_INT F77_INT& F77_RET_T F77_FUNC	(	zgehrd	,
		ZGEHRD
	)		const

F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX const F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE const F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL const F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE_CMPLX const F77_INT F77_INT& F77_RET_T F77_FUNC	(	cgeqp3	,
		CGEQP3
	)		const

F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX const F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE const F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL const F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE_CMPLX const F77_INT F77_INT& F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_INT F77_CMPLX F77_CMPLX const F77_INT F77_REAL F77_INT& F77_RET_T F77_FUNC	(	dgeqp3	,
		DGEQP3
	)		const

F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX const F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE const F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL const F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE_CMPLX const F77_INT F77_INT& F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_INT F77_CMPLX F77_CMPLX const F77_INT F77_REAL F77_INT& F77_RET_T const F77_INT F77_DBLE const F77_INT F77_INT F77_DBLE F77_DBLE const F77_INT F77_INT& F77_RET_T F77_FUNC	(	sgeqp3	,
		SGEQP3
	)		const

F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX const F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE const F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL const F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE_CMPLX const F77_INT F77_INT& F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_INT F77_CMPLX F77_CMPLX const F77_INT F77_REAL F77_INT& F77_RET_T const F77_INT F77_DBLE const F77_INT F77_INT F77_DBLE F77_DBLE const F77_INT F77_INT& F77_RET_T const F77_INT F77_REAL const F77_INT F77_INT F77_REAL F77_REAL const F77_INT F77_INT& F77_RET_T F77_FUNC	(	zgeqp3	,
		ZGEQP3
	)		const

F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX const F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE const F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL const F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE_CMPLX const F77_INT F77_INT& F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_INT F77_CMPLX F77_CMPLX const F77_INT F77_REAL F77_INT& F77_RET_T const F77_INT F77_DBLE const F77_INT F77_INT F77_DBLE F77_DBLE const F77_INT F77_INT& F77_RET_T const F77_INT F77_REAL const F77_INT F77_INT F77_REAL F77_REAL const F77_INT F77_INT& F77_RET_T const F77_INT F77_DBLE_CMPLX const F77_INT F77_INT F77_DBLE_CMPLX F77_DBLE_CMPLX const F77_INT F77_DBLE F77_INT& F77_RET_T F77_FUNC	(	cgeqrf	,
		CGEQRF
	)		const

F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX const F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE const F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL const F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE_CMPLX const F77_INT F77_INT& F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_INT F77_CMPLX F77_CMPLX const F77_INT F77_REAL F77_INT& F77_RET_T const F77_INT F77_DBLE const F77_INT F77_INT F77_DBLE F77_DBLE const F77_INT F77_INT& F77_RET_T const F77_INT F77_REAL const F77_INT F77_INT F77_REAL F77_REAL const F77_INT F77_INT& F77_RET_T const F77_INT F77_DBLE_CMPLX const F77_INT F77_INT F77_DBLE_CMPLX F77_DBLE_CMPLX const F77_INT F77_DBLE F77_INT& F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX const F77_INT F77_INT& F77_RET_T F77_FUNC	(	dgeqrf	,
		DGEQRF
	)		const

F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX const F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE const F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL const F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE_CMPLX const F77_INT F77_INT& F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_INT F77_CMPLX F77_CMPLX const F77_INT F77_REAL F77_INT& F77_RET_T const F77_INT F77_DBLE const F77_INT F77_INT F77_DBLE F77_DBLE const F77_INT F77_INT& F77_RET_T const F77_INT F77_REAL const F77_INT F77_INT F77_REAL F77_REAL const F77_INT F77_INT& F77_RET_T const F77_INT F77_DBLE_CMPLX const F77_INT F77_INT F77_DBLE_CMPLX F77_DBLE_CMPLX const F77_INT F77_DBLE F77_INT& F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX const F77_INT F77_INT& F77_RET_T const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE const F77_INT F77_INT& F77_RET_T F77_FUNC	(	sgeqrf	,
		SGEQRF
	)		const

F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX const F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE const F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL const F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE_CMPLX const F77_INT F77_INT& F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_INT F77_CMPLX F77_CMPLX const F77_INT F77_REAL F77_INT& F77_RET_T const F77_INT F77_DBLE const F77_INT F77_INT F77_DBLE F77_DBLE const F77_INT F77_INT& F77_RET_T const F77_INT F77_REAL const F77_INT F77_INT F77_REAL F77_REAL const F77_INT F77_INT& F77_RET_T const F77_INT F77_DBLE_CMPLX const F77_INT F77_INT F77_DBLE_CMPLX F77_DBLE_CMPLX const F77_INT F77_DBLE F77_INT& F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX const F77_INT F77_INT& F77_RET_T const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE const F77_INT F77_INT& F77_RET_T const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL const F77_INT F77_INT& F77_RET_T F77_FUNC	(	zgeqrf	,
		ZGEQRF
	)		const

F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX const F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE const F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL const F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE_CMPLX const F77_INT F77_INT& F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_INT F77_CMPLX F77_CMPLX const F77_INT F77_REAL F77_INT& F77_RET_T const F77_INT F77_DBLE const F77_INT F77_INT F77_DBLE F77_DBLE const F77_INT F77_INT& F77_RET_T const F77_INT F77_REAL const F77_INT F77_INT F77_REAL F77_REAL const F77_INT F77_INT& F77_RET_T const F77_INT F77_DBLE_CMPLX const F77_INT F77_INT F77_DBLE_CMPLX F77_DBLE_CMPLX const F77_INT F77_DBLE F77_INT& F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX const F77_INT F77_INT& F77_RET_T const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE const F77_INT F77_INT& F77_RET_T const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL const F77_INT F77_INT& F77_RET_T const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE_CMPLX const F77_INT F77_INT& F77_RET_T F77_FUNC	(	cgesdd	,
		CGESDD
	)

F77_RET_T F77_FUNC	(	dgesdd	,
		DGESDD
	)

F77_RET_T F77_FUNC	(	sgesdd	,
		SGESDD
	)

F77_RET_T F77_FUNC	(	zgesdd	,
		ZGESDD
	)

F77_RET_T F77_FUNC	(	cgesvd	,
		CGESVD
	)

F77_RET_T F77_FUNC	(	dgesvd	,
		DGESVD
	)

F77_RET_T F77_FUNC	(	sgesvd	,
		SGESVD
	)

F77_RET_T F77_FUNC	(	zgesvd	,
		ZGESVD
	)

F77_RET_T F77_FUNC	(	cgeesx	,
		CGEESX
	)

F77_RET_T F77_FUNC	(	dgeesx	,
		DGEESX
	)

F77_RET_T F77_FUNC	(	sgeesx	,
		SGEESX
	)

F77_RET_T F77_FUNC	(	zgeesx	,
		ZGEESX
	)

F77_RET_T F77_FUNC	(	cgeevx	,
		CGEEVX
	)

F77_RET_T F77_FUNC	(	dgeevx	,
		DGEEVX
	)

F77_RET_T F77_FUNC	(	sgeevx	,
		SGEEVX
	)

F77_RET_T F77_FUNC	(	zgeevx	,
		ZGEEVX
	)

F77_RET_T F77_FUNC	(	cgelsd	,
		CGELSD
	)		const

F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_REAL F77_REAL F77_INT F77_CMPLX const F77_INT F77_REAL F77_INT F77_INT& F77_RET_T F77_FUNC	(	dgelsd	,
		DGELSD
	)		const

F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_REAL F77_REAL F77_INT F77_CMPLX const F77_INT F77_REAL F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT F77_DBLE const F77_INT F77_INT F77_INT& F77_RET_T F77_FUNC	(	sgelsd	,
		SGELSD
	)		const

F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_REAL F77_REAL F77_INT F77_CMPLX const F77_INT F77_REAL F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT F77_DBLE const F77_INT F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL F77_INT F77_REAL const F77_INT F77_INT F77_INT& F77_RET_T F77_FUNC	(	zgelsd	,
		ZGELSD
	)		const

F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_REAL F77_REAL F77_INT F77_CMPLX const F77_INT F77_REAL F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT F77_DBLE const F77_INT F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL F77_INT F77_REAL const F77_INT F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE F77_DBLE F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE F77_INT F77_INT& F77_RET_T F77_FUNC	(	cgelsy	,
		CGELSY
	)		const

F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_REAL F77_REAL F77_INT F77_CMPLX const F77_INT F77_REAL F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT F77_DBLE const F77_INT F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL F77_INT F77_REAL const F77_INT F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE F77_DBLE F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_INT F77_REAL F77_INT F77_CMPLX const F77_INT F77_REAL F77_INT& F77_RET_T F77_FUNC	(	dgelsy	,
		DGELSY
	)		const

F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_REAL F77_REAL F77_INT F77_CMPLX const F77_INT F77_REAL F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT F77_DBLE const F77_INT F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL F77_INT F77_REAL const F77_INT F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE F77_DBLE F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_INT F77_REAL F77_INT F77_CMPLX const F77_INT F77_REAL F77_INT& F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_INT F77_DBLE F77_INT F77_DBLE const F77_INT F77_INT& F77_RET_T F77_FUNC	(	sgelsy	,
		SGELSY
	)		const

F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_REAL F77_REAL F77_INT F77_CMPLX const F77_INT F77_REAL F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT F77_DBLE const F77_INT F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL F77_INT F77_REAL const F77_INT F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE F77_DBLE F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_INT F77_REAL F77_INT F77_CMPLX const F77_INT F77_REAL F77_INT& F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_INT F77_DBLE F77_INT F77_DBLE const F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_INT F77_REAL F77_INT F77_REAL const F77_INT F77_INT& F77_RET_T F77_FUNC	(	zgelsy	,
		ZGELSY
	)		const

F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_REAL F77_REAL F77_INT F77_CMPLX const F77_INT F77_REAL F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT F77_DBLE const F77_INT F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL F77_INT F77_REAL const F77_INT F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE F77_DBLE F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_INT F77_REAL F77_INT F77_CMPLX const F77_INT F77_REAL F77_INT& F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_INT F77_DBLE F77_INT F77_DBLE const F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_INT F77_REAL F77_INT F77_REAL const F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_INT F77_DBLE F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE F77_INT& F77_RET_T F77_FUNC	(	cgetrf	,
		CGETRF
	)		const

F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_REAL F77_REAL F77_INT F77_CMPLX const F77_INT F77_REAL F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT F77_DBLE const F77_INT F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL F77_INT F77_REAL const F77_INT F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE F77_DBLE F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_INT F77_REAL F77_INT F77_CMPLX const F77_INT F77_REAL F77_INT& F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_INT F77_DBLE F77_INT F77_DBLE const F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_INT F77_REAL F77_INT F77_REAL const F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_INT F77_DBLE F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE F77_INT& F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_INT F77_INT& F77_RET_T F77_FUNC	(	dgetrf	,
		DGETRF
	)		const

F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_REAL F77_REAL F77_INT F77_CMPLX const F77_INT F77_REAL F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT F77_DBLE const F77_INT F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL F77_INT F77_REAL const F77_INT F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE F77_DBLE F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_INT F77_REAL F77_INT F77_CMPLX const F77_INT F77_REAL F77_INT& F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_INT F77_DBLE F77_INT F77_DBLE const F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_INT F77_REAL F77_INT F77_REAL const F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_INT F77_DBLE F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE F77_INT& F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_INT F77_INT& F77_RET_T const F77_INT F77_DBLE const F77_INT F77_INT F77_INT& F77_RET_T F77_FUNC	(	sgetrf	,
		SGETRF
	)		const

F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_REAL F77_REAL F77_INT F77_CMPLX const F77_INT F77_REAL F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT F77_DBLE const F77_INT F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL F77_INT F77_REAL const F77_INT F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE F77_DBLE F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_INT F77_REAL F77_INT F77_CMPLX const F77_INT F77_REAL F77_INT& F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_INT F77_DBLE F77_INT F77_DBLE const F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_INT F77_REAL F77_INT F77_REAL const F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_INT F77_DBLE F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE F77_INT& F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_INT F77_INT& F77_RET_T const F77_INT F77_DBLE const F77_INT F77_INT F77_INT& F77_RET_T const F77_INT F77_REAL const F77_INT F77_INT F77_INT& F77_RET_T F77_FUNC	(	zgetrf	,
		ZGETRF
	)		const

F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_REAL F77_REAL F77_INT F77_CMPLX const F77_INT F77_REAL F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT F77_DBLE const F77_INT F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL F77_INT F77_REAL const F77_INT F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE F77_DBLE F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_INT F77_REAL F77_INT F77_CMPLX const F77_INT F77_REAL F77_INT& F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_INT F77_DBLE F77_INT F77_DBLE const F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_INT F77_REAL F77_INT F77_REAL const F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_INT F77_DBLE F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE F77_INT& F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_INT F77_INT& F77_RET_T const F77_INT F77_DBLE const F77_INT F77_INT F77_INT& F77_RET_T const F77_INT F77_REAL const F77_INT F77_INT F77_INT& F77_RET_T const F77_INT F77_DBLE_CMPLX const F77_INT F77_INT F77_INT& F77_RET_T F77_FUNC	(	cgetri	,
		CGETRI
	)		const

F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_REAL F77_REAL F77_INT F77_CMPLX const F77_INT F77_REAL F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT F77_DBLE const F77_INT F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL F77_INT F77_REAL const F77_INT F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE F77_DBLE F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_INT F77_REAL F77_INT F77_CMPLX const F77_INT F77_REAL F77_INT& F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_INT F77_DBLE F77_INT F77_DBLE const F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_INT F77_REAL F77_INT F77_REAL const F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_INT F77_DBLE F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE F77_INT& F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_INT F77_INT& F77_RET_T const F77_INT F77_DBLE const F77_INT F77_INT F77_INT& F77_RET_T const F77_INT F77_REAL const F77_INT F77_INT F77_INT& F77_RET_T const F77_INT F77_DBLE_CMPLX const F77_INT F77_INT F77_INT& F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_CMPLX const F77_INT F77_INT& F77_RET_T F77_FUNC	(	dgetri	,
		DGETRI
	)		const

F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_REAL F77_REAL F77_INT F77_CMPLX const F77_INT F77_REAL F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT F77_DBLE const F77_INT F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL F77_INT F77_REAL const F77_INT F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE F77_DBLE F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_INT F77_REAL F77_INT F77_CMPLX const F77_INT F77_REAL F77_INT& F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_INT F77_DBLE F77_INT F77_DBLE const F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_INT F77_REAL F77_INT F77_REAL const F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_INT F77_DBLE F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE F77_INT& F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_INT F77_INT& F77_RET_T const F77_INT F77_DBLE const F77_INT F77_INT F77_INT& F77_RET_T const F77_INT F77_REAL const F77_INT F77_INT F77_INT& F77_RET_T const F77_INT F77_DBLE_CMPLX const F77_INT F77_INT F77_INT& F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_CMPLX const F77_INT F77_INT& F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE const F77_INT F77_INT& F77_RET_T F77_FUNC	(	sgetri	,
		SGETRI
	)		const

F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_REAL F77_REAL F77_INT F77_CMPLX const F77_INT F77_REAL F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT F77_DBLE const F77_INT F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL F77_INT F77_REAL const F77_INT F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE F77_DBLE F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_INT F77_REAL F77_INT F77_CMPLX const F77_INT F77_REAL F77_INT& F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_INT F77_DBLE F77_INT F77_DBLE const F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_INT F77_REAL F77_INT F77_REAL const F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_INT F77_DBLE F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE F77_INT& F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_INT F77_INT& F77_RET_T const F77_INT F77_DBLE const F77_INT F77_INT F77_INT& F77_RET_T const F77_INT F77_REAL const F77_INT F77_INT F77_INT& F77_RET_T const F77_INT F77_DBLE_CMPLX const F77_INT F77_INT F77_INT& F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_CMPLX const F77_INT F77_INT& F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE const F77_INT F77_INT& F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL const F77_INT F77_INT& F77_RET_T F77_FUNC	(	zgetri	,
		ZGETRI
	)		const

F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_REAL F77_REAL F77_INT F77_CMPLX const F77_INT F77_REAL F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT F77_DBLE const F77_INT F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL F77_INT F77_REAL const F77_INT F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE F77_DBLE F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_INT F77_REAL F77_INT F77_CMPLX const F77_INT F77_REAL F77_INT& F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_INT F77_DBLE F77_INT F77_DBLE const F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_INT F77_REAL F77_INT F77_REAL const F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_INT F77_DBLE F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE F77_INT& F77_RET_T const F77_INT F77_CMPLX const F77_INT F77_INT F77_INT& F77_RET_T const F77_INT F77_DBLE const F77_INT F77_INT F77_INT& F77_RET_T const F77_INT F77_REAL const F77_INT F77_INT F77_INT& F77_RET_T const F77_INT F77_DBLE_CMPLX const F77_INT F77_INT F77_INT& F77_RET_T F77_CMPLX const F77_INT const F77_INT F77_CMPLX const F77_INT F77_INT& F77_RET_T F77_DBLE const F77_INT const F77_INT F77_DBLE const F77_INT F77_INT& F77_RET_T F77_REAL const F77_INT const F77_INT F77_REAL const F77_INT F77_INT& F77_RET_T F77_DBLE_CMPLX const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_INT& F77_RET_T F77_FUNC	(	cgetrs	,
		CGETRS
	)

F77_RET_T F77_FUNC	(	dgetrs	,
		DGETRS
	)

F77_RET_T F77_FUNC	(	sgetrs	,
		SGETRS
	)

F77_RET_T F77_FUNC	(	zgetrs	,
		ZGETRS
	)

F77_RET_T F77_FUNC	(	cggbal	,
		CGGBAL
	)

F77_RET_T F77_FUNC	(	dggbal	,
		DGGBAL
	)

F77_RET_T F77_FUNC	(	sggbal	,
		SGGBAL
	)

F77_RET_T F77_FUNC	(	zggbal	,
		ZGGBAL
	)

F77_RET_T F77_FUNC	(	dggbak	,
		DGGBAK
	)

F77_RET_T F77_FUNC	(	sggbak	,
		SGGBAK
	)

F77_RET_T F77_FUNC	(	zggbak	,
		ZGGBAK
	)

F77_RET_T F77_FUNC	(	cggev	,
		CGGEV
	)

F77_RET_T F77_FUNC	(	dggev	,
		DGGEV
	)

F77_RET_T F77_FUNC	(	sggev	,
		SGGEV
	)

F77_RET_T F77_FUNC	(	zggev	,
		ZGGEV
	)

F77_RET_T F77_FUNC	(	dgghrd	,
		DGGHRD
	)

F77_RET_T F77_FUNC	(	zgghrd	,
		ZGGHRD
	)

F77_RET_T F77_FUNC	(	dgtsv	,
		DGTSV
	)		const

F77_RET_T const F77_INT F77_DBLE F77_DBLE F77_DBLE F77_DBLE const F77_INT F77_INT& F77_RET_T F77_FUNC	(	zgtsv	,
		ZGTSV
	)		const

F77_RET_T const F77_INT F77_DBLE F77_DBLE F77_DBLE F77_DBLE const F77_INT F77_INT& F77_RET_T const F77_INT F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE_CMPLX const F77_INT F77_INT& F77_RET_T F77_FUNC	(	dgttrf	,
		DGTTRF
	)		const

F77_RET_T const F77_INT F77_DBLE F77_DBLE F77_DBLE F77_DBLE const F77_INT F77_INT& F77_RET_T const F77_INT F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE_CMPLX const F77_INT F77_INT& F77_RET_T F77_DBLE F77_DBLE F77_DBLE F77_DBLE F77_INT F77_INT& F77_RET_T F77_FUNC	(	zgttrf	,
		ZGTTRF
	)		const

F77_RET_T const F77_INT F77_DBLE F77_DBLE F77_DBLE F77_DBLE const F77_INT F77_INT& F77_RET_T const F77_INT F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE_CMPLX const F77_INT F77_INT& F77_RET_T F77_DBLE F77_DBLE F77_DBLE F77_DBLE F77_INT F77_INT& F77_RET_T F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE_CMPLX F77_INT F77_INT& F77_RET_T F77_FUNC	(	dgttrs	,
		DGTTRS
	)

F77_RET_T F77_FUNC	(	zgttrs	,
		ZGTTRS
	)

F77_RET_T F77_FUNC	(	cheev	,
		CHEEV
	)

F77_RET_T F77_FUNC	(	zheev	,
		ZHEEV
	)

F77_RET_T F77_FUNC	(	chegv	,
		CHEGV
	)		const

F77_RET_T F77_FUNC	(	zhegv	,
		ZHEGV
	)		const

F77_RET_T F77_FUNC	(	cherk	,
		CHERK
	)

F77_RET_T F77_FUNC	(	zherk	,
		ZHERK
	)

F77_RET_T F77_FUNC	(	dhgeqz	,
		DHGEQZ
	)

F77_RET_T F77_FUNC	(	zhgeqz	,
		ZHGEQZ
	)

F77_RET_T F77_FUNC	(	xilaenv	,
		XILAENV
	)		const

F77_RET_T F77_FUNC	(	dlag2	,
		DLAG2
	)		const

F77_RET_T F77_FUNC	(	xdlamch	,
		XDLAMCH
	)

F77_RET_T F77_FUNC	(	xclange	,
		XCLANGE
	)

F77_RET_T F77_FUNC	(	xdlange	,
		XDLANGE
	)

F77_RET_T F77_FUNC	(	xslange	,
		XSLANGE
	)

F77_RET_T F77_FUNC	(	xzlange	,
		XZLANGE
	)

F77_RET_T F77_FUNC	(	clartg	,
		CLARTG
	)		const

F77_RET_T const F77_CMPLX F77_REAL F77_CMPLX F77_CMPLX* F77_RET_T F77_FUNC	(	dlartg	,
		DLARTG
	)		const

F77_RET_T const F77_CMPLX F77_REAL F77_CMPLX F77_CMPLX* F77_RET_T const F77_DBLE F77_DBLE F77_DBLE F77_DBLE& F77_RET_T F77_FUNC	(	slartg	,
		SLARTG
	)		const

F77_RET_T const F77_CMPLX F77_REAL F77_CMPLX F77_CMPLX* F77_RET_T const F77_DBLE F77_DBLE F77_DBLE F77_DBLE& F77_RET_T const F77_REAL F77_REAL F77_REAL F77_REAL& F77_RET_T F77_FUNC	(	zlartg	,
		ZLARTG
	)		const

F77_RET_T const F77_CMPLX F77_REAL F77_CMPLX F77_CMPLX* F77_RET_T const F77_DBLE F77_DBLE F77_DBLE F77_DBLE& F77_RET_T const F77_REAL F77_REAL F77_REAL F77_REAL& F77_RET_T const F77_DBLE_CMPLX F77_DBLE F77_DBLE_CMPLX F77_DBLE_CMPLX* F77_RET_T F77_FUNC	(	dorghr	,
		DORGHR
	)		const

F77_RET_T const F77_CMPLX F77_REAL F77_CMPLX F77_CMPLX* F77_RET_T const F77_DBLE F77_DBLE F77_DBLE F77_DBLE& F77_RET_T const F77_REAL F77_REAL F77_REAL F77_REAL& F77_RET_T const F77_DBLE_CMPLX F77_DBLE F77_DBLE_CMPLX F77_DBLE_CMPLX* F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE const F77_INT F77_INT& F77_RET_T F77_FUNC	(	sorghr	,
		SORGHR
	)		const

F77_RET_T const F77_CMPLX F77_REAL F77_CMPLX F77_CMPLX* F77_RET_T const F77_DBLE F77_DBLE F77_DBLE F77_DBLE& F77_RET_T const F77_REAL F77_REAL F77_REAL F77_REAL& F77_RET_T const F77_DBLE_CMPLX F77_DBLE F77_DBLE_CMPLX F77_DBLE_CMPLX* F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE const F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL const F77_INT F77_INT& F77_RET_T F77_FUNC	(	dorgqr	,
		DORGQR
	)		const

F77_RET_T const F77_CMPLX F77_REAL F77_CMPLX F77_CMPLX* F77_RET_T const F77_DBLE F77_DBLE F77_DBLE F77_DBLE& F77_RET_T const F77_REAL F77_REAL F77_REAL F77_REAL& F77_RET_T const F77_DBLE_CMPLX F77_DBLE F77_DBLE_CMPLX F77_DBLE_CMPLX* F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE const F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL const F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE const F77_INT F77_INT& F77_RET_T F77_FUNC	(	sorgqr	,
		SORGQR
	)		const

F77_RET_T const F77_CMPLX F77_REAL F77_CMPLX F77_CMPLX* F77_RET_T const F77_DBLE F77_DBLE F77_DBLE F77_DBLE& F77_RET_T const F77_REAL F77_REAL F77_REAL F77_REAL& F77_RET_T const F77_DBLE_CMPLX F77_DBLE F77_DBLE_CMPLX F77_DBLE_CMPLX* F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE const F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL const F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE const F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL const F77_INT F77_INT& F77_RET_T F77_FUNC	(	dpbcon	,
		DPBCON
	)

F77_RET_T F77_FUNC	(	zpbcon	,
		ZPBCON
	)

F77_RET_T F77_FUNC	(	dpbtrf	,
		DPBTRF
	)

F77_RET_T F77_FUNC	(	zpbtrf	,
		ZPBTRF
	)

F77_RET_T F77_FUNC	(	dpbtrs	,
		DPBTRS
	)

F77_RET_T F77_FUNC	(	zpbtrs	,
		ZPBTRS
	)

F77_RET_T F77_FUNC	(	cpocon	,
		CPOCON
	)

F77_RET_T F77_FUNC	(	dpocon	,
		DPOCON
	)

F77_RET_T F77_FUNC	(	spocon	,
		SPOCON
	)

F77_RET_T F77_FUNC	(	zpocon	,
		ZPOCON
	)

F77_RET_T F77_FUNC	(	cpotrf	,
		CPOTRF
	)

F77_RET_T F77_FUNC	(	dpotrf	,
		DPOTRF
	)

F77_RET_T F77_FUNC	(	spotrf	,
		SPOTRF
	)

F77_RET_T F77_FUNC	(	zpotrf	,
		ZPOTRF
	)

F77_RET_T F77_FUNC	(	cpotri	,
		CPOTRI
	)

F77_RET_T F77_FUNC	(	dpotri	,
		DPOTRI
	)

F77_RET_T F77_FUNC	(	spotri	,
		SPOTRI
	)

F77_RET_T F77_FUNC	(	zpotri	,
		ZPOTRI
	)

F77_RET_T F77_FUNC	(	spotrs	,
		SPOTRS
	)

F77_RET_T F77_FUNC	(	cpotrs	,
		CPOTRS
	)

F77_RET_T F77_FUNC	(	dpotrs	,
		DPOTRS
	)

F77_RET_T F77_FUNC	(	zpotrs	,
		ZPOTRS
	)

F77_RET_T F77_FUNC	(	dptsv	,
		DPTSV
	)		const

F77_RET_T const F77_INT F77_DBLE F77_DBLE F77_DBLE const F77_INT F77_INT& F77_RET_T F77_FUNC	(	zptsv	,
		ZPTSV
	)		const

F77_RET_T const F77_INT F77_DBLE F77_DBLE F77_DBLE const F77_INT F77_INT& F77_RET_T const F77_INT F77_DBLE F77_DBLE_CMPLX F77_DBLE_CMPLX const F77_INT F77_INT& F77_RET_T F77_FUNC	(	zrsf2csf	,
		ZRSF2CSF
	)		const

F77_RET_T const F77_INT F77_DBLE F77_DBLE F77_DBLE const F77_INT F77_INT& F77_RET_T const F77_INT F77_DBLE F77_DBLE_CMPLX F77_DBLE_CMPLX const F77_INT F77_INT& F77_RET_T F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE F77_DBLE* F77_RET_T F77_FUNC	(	crsf2csf	,
		CRSF2CSF
	)		const

F77_RET_T const F77_INT F77_DBLE F77_DBLE F77_DBLE const F77_INT F77_INT& F77_RET_T const F77_INT F77_DBLE F77_DBLE_CMPLX F77_DBLE_CMPLX const F77_INT F77_INT& F77_RET_T F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE F77_DBLE* F77_RET_T F77_CMPLX F77_CMPLX F77_REAL F77_REAL* F77_RET_T F77_FUNC	(	dsyev	,
		DSYEV
	)

F77_RET_T F77_FUNC	(	ssyev	,
		SSYEV
	)

F77_RET_T F77_FUNC	(	dsygv	,
		DSYGV
	)		const

F77_RET_T F77_FUNC	(	ssygv	,
		SSYGV
	)		const

F77_RET_T F77_FUNC	(	csyrk	,
		CSYRK
	)

F77_RET_T F77_FUNC	(	dsyrk	,
		DSYRK
	)

F77_RET_T F77_FUNC	(	ssyrk	,
		SSYRK
	)

F77_RET_T F77_FUNC	(	zsyrk	,
		ZSYRK
	)

F77_RET_T F77_FUNC	(	dtgevc	,
		DTGEVC
	)

F77_RET_T F77_FUNC	(	ztgevc	,
		ZTGEVC
	)

F77_RET_T F77_FUNC	(	ctrcon	,
		CTRCON
	)

F77_RET_T F77_FUNC	(	dtrcon	,
		DTRCON
	)

F77_RET_T F77_FUNC	(	strcon	,
		STRCON
	)

F77_RET_T F77_FUNC	(	ztrcon	,
		ZTRCON
	)

F77_RET_T F77_FUNC	(	ctrsen	,
		CTRSEN
	)

F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_INT F77_REAL F77_REAL F77_CMPLX const F77_INT F77_INT& F77_RET_T F77_FUNC	(	dtrsen	,
		DTRSEN
	)

F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_INT F77_REAL F77_REAL F77_CMPLX const F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT F77_DBLE F77_DBLE F77_DBLE const F77_INT F77_INT const F77_INT F77_INT& F77_RET_T F77_FUNC	(	strsen	,
		STRSEN
	)

F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_INT F77_REAL F77_REAL F77_CMPLX const F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT F77_DBLE F77_DBLE F77_DBLE const F77_INT F77_INT const F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL F77_INT F77_REAL F77_REAL F77_REAL const F77_INT F77_INT const F77_INT F77_INT& F77_RET_T F77_FUNC	(	ztrsen	,
		ZTRSEN
	)

F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_INT F77_REAL F77_REAL F77_CMPLX const F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_INT F77_DBLE F77_DBLE F77_DBLE const F77_INT F77_INT const F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_REAL const F77_INT F77_REAL const F77_INT F77_REAL F77_REAL F77_INT F77_REAL F77_REAL F77_REAL const F77_INT F77_INT const F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_INT F77_DBLE F77_DBLE F77_DBLE_CMPLX const F77_INT F77_INT& F77_RET_T F77_FUNC	(	ctrsyl	,
		CTRSYL
	)

F77_RET_T F77_FUNC	(	dtrsyl	,
		DTRSYL
	)

F77_RET_T F77_FUNC	(	strsyl	,
		STRSYL
	)

F77_RET_T F77_FUNC	(	ztrsyl	,
		ZTRSYL
	)

F77_RET_T F77_FUNC	(	ctrtri	,
		CTRTRI
	)

F77_RET_T F77_FUNC	(	dtrtri	,
		DTRTRI
	)

F77_RET_T F77_FUNC	(	strtri	,
		STRTRI
	)

F77_RET_T F77_FUNC	(	ztrtri	,
		ZTRTRI
	)

F77_RET_T F77_FUNC	(	ctrtrs	,
		CTRTRS
	)

F77_RET_T F77_FUNC	(	dtrtrs	,
		DTRTRS
	)

F77_RET_T F77_FUNC	(	strtrs	,
		STRTRS
	)

F77_RET_T F77_FUNC	(	ztrtrs	,
		ZTRTRS
	)

F77_RET_T F77_FUNC	(	cunghr	,
		CUNGHR
	)		const

F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX const F77_INT F77_INT& F77_RET_T F77_FUNC	(	zunghr	,
		ZUNGHR
	)		const

F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX const F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE_CMPLX const F77_INT F77_INT& F77_RET_T F77_FUNC	(	cungqr	,
		CUNGQR
	)		const

F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX const F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE_CMPLX const F77_INT F77_INT& F77_RET_T const F77_INT const F77_INT F77_CMPLX const F77_INT F77_CMPLX F77_CMPLX const F77_INT F77_INT& F77_RET_T F77_FUNC	(	zungqr	,
		ZUNGQR
	)		const

Variable Documentation

F77_RET_T F77_INT const F77_INT const F77_DBLE_CMPLX * A

Definition at line 653 of file lo-lapack-proto.h.

Referenced by convert_to_int_array(), convert_to_octave_idx_type_array(), Fcolloc(), CollocWt::first(), SparseMatrix::fsolve(), SparseComplexMatrix::fsolve(), G__glpk__(), Gccolamd(), Gcolamd(), Gsymbfact(), octave::math::sparse_chol< chol_type >::sparse_chol_rep< chol_type >::init(), maybe_update_column(), CollocWt::operator=(), octave::math::sparse_qr< SPARSE_T >::sparse_qr_rep< SPARSE_T >::sparse_qr_rep(), and Vt102Emulation::tau().

F77_RET_T const F77_INT const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX* ALPHA

Definition at line 944 of file lo-lapack-proto.h.

F77_RET_T const F77_INT const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE* ALPHAI

Definition at line 926 of file lo-lapack-proto.h.

F77_RET_T const F77_INT const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE* ALPHAR

Definition at line 926 of file lo-lapack-proto.h.

F77_RET_T F77_INT const F77_INT const F77_DBLE_CMPLX const F77_INT const F77_DBLE_CMPLX * B

Definition at line 653 of file lo-lapack-proto.h.

Referenced by dmsolve_extract(), Fcolloc(), SparseMatrix::fsolve(), SparseComplexMatrix::fsolve(), G__glpk__(), Gsymrcm(), CollocWt::operator=(), CollocWt::second(), and octave::math::sparse_qr< SPARSE_T >::sparse_qr_rep< SPARSE_T >::wide_solve().

F77_RET_T const F77_INT const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE_CMPLX * BETA

Definition at line 926 of file lo-lapack-proto.h.

F77_RET_T const F77_INT const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE_CMPLX* CQ

Definition at line 944 of file lo-lapack-proto.h.

F77_RET_T F77_INT const F77_INT const F77_DBLE_CMPLX const F77_INT const F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT F77_INT F77_DBLE_CMPLX* CWORK

Definition at line 1355 of file lo-lapack-proto.h.

F77_RET_T const F77_INT const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX* CZ

Definition at line 944 of file lo-lapack-proto.h.

F77_RET_T const F77_INT const F77_INT const F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_INT& F77_CHAR_ARG_LEN_DECL F77_CHAR_ARG_LEN_DECL F77_CHAR_ARG_LEN_DECL

Definition at line 37 of file lo-lapack-proto.h.

F77_RET_T F77_CONST_CHAR_ARG_DECL

Definition at line 121 of file lo-lapack-proto.h.

F77_RET_T const F77_INT const F77_INT const F77_INT & IHI

Definition at line 653 of file lo-lapack-proto.h.

F77_RET_T const F77_INT const F77_INT & ILO

Definition at line 653 of file lo-lapack-proto.h.

F77_RET_T F77_INT const F77_INT const F77_DBLE_CMPLX const F77_INT & LDA

Definition at line 653 of file lo-lapack-proto.h.

F77_RET_T F77_INT const F77_INT const F77_DBLE_CMPLX const F77_INT const F77_DBLE_CMPLX const F77_INT & LDB

Definition at line 653 of file lo-lapack-proto.h.

F77_RET_T const F77_INT const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE_CMPLX const F77_INT & LDQ

Definition at line 786 of file lo-lapack-proto.h.

F77_RET_T const F77_INT const F77_INT const F77_INT const F77_DBLE const F77_DBLE F77_INT F77_DBLE_CMPLX const F77_INT & LDV

Definition at line 695 of file lo-lapack-proto.h.

F77_RET_T F77_INT const F77_INT const F77_DBLE_CMPLX const F77_INT const F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT & LDVL

Definition at line 1341 of file lo-lapack-proto.h.

F77_RET_T F77_INT const F77_INT const F77_DBLE_CMPLX const F77_INT const F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT & LDVR

Definition at line 1341 of file lo-lapack-proto.h.

F77_RET_T const F77_INT const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT & LDZ

Definition at line 786 of file lo-lapack-proto.h.

F77_RET_T const F77_INT const F77_INT const F77_INT const F77_DBLE * LSCALE

Definition at line 653 of file lo-lapack-proto.h.

F77_RET_T const F77_INT const F77_INT const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX F77_DBLE_CMPLX F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT & LWORK

Definition at line 926 of file lo-lapack-proto.h.

F77_RET_T F77_INT const F77_INT const F77_DBLE_CMPLX const F77_INT const F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT F77_INT & M

Definition at line 695 of file lo-lapack-proto.h.

Referenced by EigsComplexNonSymmetricMatrix(), EigsComplexNonSymmetricMatrixShift(), EigsRealNonSymmetricMatrix(), EigsRealNonSymmetricMatrixShift(), EigsRealSymmetricMatrix(), EigsRealSymmetricMatrixShift(), lin_interpn(), ltsolve(), and utsolve().

F77_RET_T F77_INT const F77_INT const F77_DBLE_CMPLX const F77_INT const F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT & MM

Definition at line 1341 of file lo-lapack-proto.h.

F77_RET_T F77_INT const F77_INT & N

Definition at line 653 of file lo-lapack-proto.h.

Referenced by octave::math::sparse_qr< SPARSE_T >::sparse_qr_rep< SPARSE_T >::C(), calc_degrees(), find_starting_node(), Gsymrcm(), MessageDialog::MessageDialog(), octave::math::sparse_qr< SPARSE_T >::sparse_qr_rep< SPARSE_T >::ok(), octave::math::sparse_qr< SPARSE_T >::sparse_qr_rep< SPARSE_T >::P(), octave::math::sparse_qr< SPARSE_T >::sparse_qr_rep< SPARSE_T >::Q(), octave::math::sparse_qr< SPARSE_T >::sparse_qr_rep< SPARSE_T >::R(), octave::math::sparse_qr< SPARSE_T >::sparse_qr_rep< SPARSE_T >::sparse_qr_rep(), octave::math::sparse_qr< SPARSE_T >::sparse_qr_rep< SPARSE_T >::tall_solve(), Vt102Emulation::tau(), transpose(), octave::math::sparse_qr< SPARSE_T >::sparse_qr_rep< SPARSE_T >::V(), octave::math::sparse_qr< SPARSE_T >::sparse_qr_rep< SPARSE_T >::wide_solve(), and octave::math::sparse_qr< SPARSE_T >::sparse_qr_rep< SPARSE_T >::~sparse_qr_rep().

F77_RET_T const F77_INT const F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE F77_DBLE F77_DBLE F77_DBLE * Q

Definition at line 786 of file lo-lapack-proto.h.

Referenced by octave::math::sparse_lu< lu_type >::col_perm(), EigsComplexNonSymmetricMatrixShift(), EigsRealNonSymmetricMatrixShift(), EigsRealSymmetricMatrixShift(), find_starting_node(), Gsymrcm(), octave::math::sparse_chol< chol_type >::inverse(), SparseComplexMatrix::inverse(), SparseMatrix::inverse(), octave::math::sparse_lu< lu_type >::operator=(), octave::math::sparse_lu< lu_type >::Pc(), octave::math::sparse_lu< lu_type >::Pc_mat(), octave::math::sparse_lu< lu_type >::Pc_vec(), and xpow().

F77_RET_T const F77_INT const F77_INT const F77_INT const F77_DBLE const F77_DBLE * RSCALE

Definition at line 653 of file lo-lapack-proto.h.

F77_RET_T F77_INT const F77_INT const F77_DBLE_CMPLX const F77_INT const F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT const F77_INT F77_INT F77_DBLE_CMPLX F77_DBLE * RWORK

Definition at line 944 of file lo-lapack-proto.h.

F77_RET_T const F77_INT const F77_DBLE const F77_INT const F77_DBLE& SAFMIN

Definition at line 975 of file lo-lapack-proto.h.

F77_RET_T const F77_INT const F77_DBLE const F77_INT const F77_DBLE F77_DBLE& SCALE1

Definition at line 975 of file lo-lapack-proto.h.

F77_RET_T const F77_INT const F77_DBLE const F77_INT const F77_DBLE F77_DBLE F77_DBLE& SCALE2

Definition at line 975 of file lo-lapack-proto.h.

F77_RET_T F77_INT * SELECT

Definition at line 1341 of file lo-lapack-proto.h.

F77_RET_T const F77_INT const F77_INT const F77_INT const F77_DBLE const F77_DBLE F77_INT F77_DBLE_CMPLX * V

Definition at line 695 of file lo-lapack-proto.h.

Referenced by convert_chars(), convert_ints(), bp_table::dbstop_process_map_args(), F__lin_interpn__(), Fmgorth(), null(), pprsc(), Matrix::pseudo_inverse(), FloatMatrix::pseudo_inverse(), ComplexMatrix::pseudo_inverse(), and FloatComplexMatrix::pseudo_inverse().

F77_RET_T F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE* VL

Definition at line 1341 of file lo-lapack-proto.h.

F77_RET_T F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE* VR

Definition at line 1341 of file lo-lapack-proto.h.

F77_RET_T const F77_INT const F77_DBLE const F77_INT const F77_DBLE F77_DBLE F77_DBLE F77_DBLE F77_DBLE F77_DBLE& WI

Definition at line 975 of file lo-lapack-proto.h.

F77_RET_T F77_INT const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT F77_DBLE const F77_INT const F77_INT F77_INT F77_DBLE * WORK

Definition at line 653 of file lo-lapack-proto.h.

F77_RET_T const F77_INT const F77_DBLE const F77_INT const F77_DBLE F77_DBLE F77_DBLE F77_DBLE& WR1

Definition at line 975 of file lo-lapack-proto.h.

F77_RET_T const F77_INT const F77_DBLE const F77_INT const F77_DBLE F77_DBLE F77_DBLE F77_DBLE F77_DBLE& WR2

Definition at line 975 of file lo-lapack-proto.h.

F77_RET_T F77_INT const F77_INT const F77_DBLE_CMPLX const F77_INT const F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX* xVL

Definition at line 1355 of file lo-lapack-proto.h.

F77_RET_T F77_INT const F77_INT const F77_DBLE_CMPLX const F77_INT const F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX const F77_INT F77_DBLE_CMPLX* xVR

Definition at line 1355 of file lo-lapack-proto.h.

OCTAVE_EXPORT octave_value_list Z

Definition at line 786 of file lo-lapack-proto.h.

Referenced by drawcn(), F__contourc__(), mark_facets(), and qp().